Developing FPGA-accelerated cloud applications with SDAccel: Theory
Developing FPGA-accelerated cloud applications with SDAccel: Theory
This course, which is the third one of a “series”, is for anyone passionate about learning the theory on how to develop FPGA-accelerated applications with SDAccel.
Introduction to FPGA systems
This series of courses introduces students to the concept of Reconfigurable FPGA-based Systems, by discussing their overall architecture and companion design flows. The goal is to present to the students the methodological approaches for the design of such systems, showing also real industrial tools, examples and common practices.
See the full seriesCourse description
We are entering an era in which technological progress induces paradigm shifts in computing.
As a tradeoff between the two extreme characteristics of GPP and ASIC, we can find a new concept, a new idea of computing... the reconfigurable computing, which has combined the advantages of both the previous worlds. Within this context, we can say that reconfigurable computing will widely, pervasively, and gradually impact human lives. Hence, it is time that we focus on how reconfigurable computing and reconfigurable system design techniques are to be utilised for building applications.
On one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance.
Within this context, the Xilinx SDx tools, including the SDAccel environment, the SDSoC environment, and Vivado HLS, provide an out-of-the-box experience for system programmers looking to partition elements of a software application to run in an FPGA-based hardware element, and having that hardware work seamlessly with the rest of the application running in a processor or embedded processor.
The out-of-the-box experience will provide interesting and, let us say, “good enough” results for many applications.
However, this may not be true for you, you may be looking for better performance, data throughput, reduced latency, or to reduce the resources usage...
This course is focusing on this. After introducing you to the FPGAs we are going to dig more into the details on how to use Xilinx SDAccel providing you also with working examples on how to optimize the hardware logic to obtain the best of of your hardware implementations. In this case, certain attributes, directives, or pragmas, can be used to direct the compilation and synthesis of the hardware kernel, or to optimise the function of the data mover operating between the processor and the hardware logic.
Furthermore, in this course we are going to focus on distributed, heterogeneous infrastructures, presenting how to bring your solutions to life by using the Amazon EC2 F1 instances.
Intended Learning Outcomes
Prerequisites
This course follows the previous ones “FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing” and “FPGA computing systems: Partial Dynamic Reconfiguration”. Within this context no specific background knowledge is requested. Anyone with moderate computer experience should be able to master the materials in this course.
Activities
The forum of this MOOC is freely accessible and participation is not guided; you can use it to compare yourself with other participants, or to discuss course contents with them.
Topic outline
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Week 1 provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.
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Week 2 is going to see how this language has been used in SDAccel and the main "components" of this toolchain.
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Week 3 will first understand how an FPGA is working, also from a computational point of view. We will briefly compare a processor sequential execution with the intrinsic parallel nature of an FPGA implementation.Furthermore, within this week we are going to familiarise ourselves with the application optimisation flow.
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Week 4 will provide a bird's eye view on the available SDAccel optimisations. The presented optimisations are not the only available ones, but they are more a list of recommendations to optimise the performance of an OpenCL application that have to be used as a starting point for ideas to consider or investigate further.
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Week 5 will focus on four specific optimisations: loop unrolling, loop pipelining, array partitioning optimisation and the host optimisations.
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Week 6 will introduce FPGA-augmented cloud infrastructures.
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Assessment
Your final grade for the course will be based on the results of your answers to the graded quizzes. You have unlimited attempts at each quiz, but you must wait 5 minutes before you can try again. You will have successfully completed the course if you achieve 60% (or more) of the total course score. The maximum score possible for each quiz is given at the top of the quiz. You can see your score in the quiz on your last attempt or on the 'Grades' page.
Certificate of accomplishment
You must be registered in POK through Politecnico di Milano personal account to obtain the Certificate of Accomplishment. It will be released to anyone who successfully completed the course by achieving at least 60% of the total score in the graded quizzes and filling the final survey.
You will be able to download the Certificate of Accomplishment directly from Politecnico di Milano web services.
The Certificate of Accomplishment does not confer any academic credit, grade or degree.
Information about fees and access to materials
You can access the course completely online and absolutely free of charge.
Course faculty
Lorenzo Di Tucci
Teacher
Lorenzo is a Ph.D. Student at Politecnico di Milano and co-founder of Huxelerate.
He received his Bachelor’s and Master’s degrees in Computer Engineering from Politecnico di Milano in 2013 and 2016 respectively. In 2016 he received a Master of Science in Computer Science from the University of Illinois at Chicago.
Lorenzo has been a Research Assistant at the University of Illinois at Chicago, Visiting Researcher at Lawrence Berkeley National Laboratory in Berkeley (CA) and Rocca Fellow at Massachusetts Institute of Technology in Cambridge (MA). His research interests float around FPGA design, High-Performance Computing, and Hardware Architectures.
Marco Domenico Santambrogio
Teacher
He is an Associate professor at Politecnico di Milano and a Research Affiliate with the CSAIL at MIT. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), his second M. Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). Dr. Santambrogio was a postdoc fellow at CSAIL, MIT, and he has also held visiting positions at the Department of Electrical Engineering and Computer Science of the Northwestern University (2006 and 2007) and Heinz Nixdorf Institut (2006).
Marco D. Santambrogio is a senior member of the IEEE. Marco D. Santambrogio is a senior member of both the IEEE and ACM, he is member of the IEEE Computer Society (CS) and the IEEE Circuits and Systems Society (CAS). He is or has been member of different program committees of electronic design automation conferences, among which: DAC, DATE, CODES+ISSS, FPL, RAW, EUC, IFIP VLSI Conference.
He has been with the Micro Architectures Laboratory at the Politecnico di Milano, where he founded the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, in charge of the laboratory.
Contact details
If you have any enquiries about the course or if you need technical assistance please contact pok@polimi.it. For further information, see FAQ page.