FPGA computing systems: Partial Dynamic Reconfiguration
FPGA computing systems: Partial Dynamic Reconfiguration
The course introduces students to the concept of Reconfigurable FPGA-based Systems, by discussing their overall architecture and companion design flows. The goal is to present to the students the methodological approaches for the design of such systems, showing also real industrial tools, examples and common practices.
Introduction to FPGA systems
This series of courses introduces students to the concept of Reconfigurable FPGA-based Systems, by discussing their overall architecture and companion design flows. The goal is to present to the students the methodological approaches for the design of such systems, showing also real industrial tools, examples and common practices.
See the full seriesCourse description
New application domains demand ever increasing adaptability and performance. In order to cope with changing user requirements, improvements in system features, changing protocol and data-coding standards, and demands for support of a variety of different user applications, many emerging applications in communication, computing and consumer electronics demand that their functionality stays flexible after the system has been manufactured. Reconfigurable Systems-on-a-Chips (SoCs) employing different microprocessor cores and different types of reconfigurable fabrics are one attractive solution for these domains. The increasing prominence of reconfigurable devices within such systems requires HW/SW co-design for SoCs to address the trade-off between software execution and reconfigurable hardware acceleration. Dynamic reconfiguration capabilities of current reconfigurable devices create an additional dimension in the temporal domain. During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration.
The course will introduce the student with the concept of reconfigurability in FPGAs, presenting the available mechanisms and technologies at the device level and the tools and design methodologies required to design reconfigurable FPGA-based systems. The course will present the different aspects of the design of FPGA-based reconfigurable systems, focusing in particular on dynamically self-reconfigurable systems. The design methodologies and tools required to design a dynamically-reconfigurable system will be introduced and described, together with the problems that need to be considered.
After this course you will be able to:
- describe why reconfigurable computing can be seen as an extension of the HW/SW codesign;
- illustrate the reconfigurable computing “taxonomy”;
- summarize the main concepts/terms introduced with respect to a reconfigurable computing scenario;
- understand how a design flow to design and implement a reconfigurable system is working.
Once a student completes this course, he will be ready to take more advanced FPGA courses.
Intended Learning Outcomes
Prerequisites
This course follows the previous one "FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing". Within this context no specific background knowledge is requested. Anyone with moderate computer experience should be able to master the materials in this course.
Activities
The forum of this MOOC is freely accessible and participation is not guided; you can use it to compare yourself with other participants, or to discuss course contents with them.
A Bibliography section is available, where you can find a list of resources that can help you in deepening the topics of the course.
Topic outline
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Week 1 will learn to name the 5 Ws with respect to a reconfigurable hardware context, to describe why reconfigurable computing can be seen as an extension of the HW/SW codesign, to Illustrate the reconfigurable computing “taxonomy” and to summarize the main concepts/terms introduced with respect to a reconfigurable computing scenario.
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Week 2 is focused on the discussion about scenarios where Partial Dynamic Reconfiguration can be effective, on the discussion about how the reconfiguration overhead can be “hidden” and on the definition, based on the specific scenario, of which techniques can be used to deal with the overhead introduced by the PDR.
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Week 3 will compare different flows to realize a reconfigurable system, you will understand how a design flow to design and implement a reconfigurable system is working, and you will identify and explain the phases composing a design flow for FPGA-based system.
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Week 4 will learn to understand the rationale behind the choice of moving towards reconfigurable cloud solutions and to justify the idea of moving from a single FPGA-based system to a distributed scenario.
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Assessment
Your final grade for the course will be based on the results of your answers to the graded quizzes. You have unlimited attempts at each quiz, but you must wait 5 minutes before you can try again. You will have successfully completed the course if you achieve 60% (or more) of the total course score. The maximum score possible for each quiz is given at the top of the quiz. You can see your score in the quiz on your last attempt or on the 'Grades' page.
Certificate of accomplishment
You must be registered in POK through Politecnico di Milano personal account to obtain the Certificate of Accomplishment. It will be released to anyone who successfully completed the course by achieving at least 60% of the total score in the graded quizzes and filling the final survey.
You will be able to download the Certificate of Accomplishment directly from Politecnico di Milano web services.
The Certificate of Accomplishment does not confer any academic credit, grade or degree.
Information about fees and access to materials
You can access the course completely online and absolutely free of charge.
Course faculty
Marco Domenico Santambrogio
Teacher
He is an Associate professor at Politecnico di Milano and a Research Affiliate with the CSAIL at MIT. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), his second M. Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). Dr. Santambrogio was a postdoc fellow at CSAIL, MIT, and he has also held visiting positions at the Department of Electrical Engineering and Computer Science of the Northwestern University (2006 and 2007) and Heinz Nixdorf Institut (2006).
Marco D. Santambrogio is a senior member of the IEEE. Marco D. Santambrogio is a senior member of both the IEEE and ACM, he is member of the IEEE Computer Society (CS) and the IEEE Circuits and Systems Society (CAS). He is or has been member of different program committees of electronic design automation conferences, among which: DAC, DATE, CODES+ISSS, FPL, RAW, EUC, IFIP VLSI Conference.
He has been with the Micro Architectures Laboratory at the Politecnico di Milano, where he founded the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, in charge of the laboratory.
Contact details
If you have any enquiries about the course or if you need technical assistance please contact pok@polimi.it. For further information, see FAQ page.