FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing
FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing
This course, which is the first one of a “series”, is for anyone passionate in learning how a hardware component can be adapted at runtime to better respond to users/environment needs. This adaptation can be provided by the designers, or it can be an embedded characteristic of the system itself.
Introduction to FPGA systems
This series of courses introduces students to the concept of Reconfigurable FPGA-based Systems, by discussing their overall architecture and companion design flows. The goal is to present to the students the methodological approaches for the design of such systems, showing also real industrial tools, examples and common practices.
See the full seriesCourse description
Nowadays the complexity of computing systems is skyrocketing. Programmers have to deal with extremely powerful computing systems that take time and considerable skills to be instructed to perform at their best. It is clear that it is not feasible to rely on human intervention to tune a system: conditions change frequently, rapidly, and unpredictably. It would be desirable to have the system automatically adapt to the mutating environment.
This course analyzes the stated problem, embraces a radically new approach, and it introduces how software and hardware systems ca ben adjusted during execution. By doing this, we are going to introduce the Field Programmable Gate Arrays (FPGA) technologies and how they can be (re)configured.
Total workload of the course: 20 hours
This MOOC is provided by Politecnico di Milano.
Intended Learning Outcomes
After this course you will be able to:
- explain the rationale behind an FPGA-based reconfigurable computing system;
- know the importance of FPGAs and of the reconfigurable computing technologies;
- compare domains to understand if they can benefit from a “reconfigurable approach”;
- describe the main components used to “define” an FPGA and how a system can be implemented on it.
In broad terms, the participant will develop the learning outcomes in the areas of: ESCO: computer technology, ESCO: electronics, ESCO: use ICT systems, ESCO: computational biology
Prerequisites
This is an introductory course to FPGA, therefore within this context no specific background knowledge is requested. Anyone with moderate computer experience should be able to master the materials in this course.
Activities
Over and above consulting the content, in the form of videos and other web-based resources, you will have the opportunity to discuss course topics and to share ideas with your peers in the Forum of this MOOC. The forum of this MOOC is freely accessible, and participation is not guided; you can use it to compare yourself with other participants, or to discuss course contents with them.
A Bibliography section is available, where you can find a list of resources that can help you in deepening the topics of the course.
Section outline
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Week 1 will learn to give examples of different kinds of reconfigurations, to compare domains to understand if they can benefit from a “reconfigurable approach”, to describe the differences in between Programmable System-on-Chip and Programmable System-on-Multiple Chip and to learn the importance of FPGAs and of the reconfigurable computing technologies.
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Week 2 will able to define reconfigurable computing, to explain the rationale behind an FPGA-based reconfigurable computing system and to defend the needs to introduce the Partial Dynamic Reconfiguration.
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Week 3 is focused on the description of the main components used to “define” an FPGA, on the explanation of how an FPGA can be configured and the explanation of what a bitstream is used for.
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Week 4 will learn to combine design phases to properly implement a circuit on an FPGA, to design a circuit on an FPGA and you will learn how a circuit can be implemented on an FPGA.
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Video transcripts Folder
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Bibliography Page
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Assessment
Your final grade for the course will be based on the results of your answers to the assessed quizzes. You have an unlimited number of attempts at each quiz, but you must wait 15 minutes before you can try again. You will have successfully completed the course if you score 60% (or higher) in each one of the assessed quizzes. The maximum score possible for each quiz is given at the beginning of the quiz. You can view your score in the quiz on your last attempt or on the 'Grades' page.
Certificate
You can achieve a certificate in the form of an Open Badge for this course, if you reach at least 60% of the total score in each one of the assessed quizzes and fill in the final survey.
Once you have completed the required tasks, you will be able to access ‘Get the Open Badge’ and start issuing the badge. Instructions on how to access the badge will be sent to your e-mail address.
The Badge does not confer any academic credit, grade or degree.
Information about fees and access to materials
You can access the course completely online and absolutely free of charge.
Course faculty
Marco Domenico Santambrogio
Teacher
He is an Associate professor at Politecnico di Milano and a Research Affiliate with the CSAIL at MIT. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), his second M. Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). Dr. Santambrogio was a postdoc fellow at CSAIL, MIT, and he has also held visiting positions at the Department of Electrical Engineering and Computer Science of the Northwestern University (2006 and 2007) and Heinz Nixdorf Institut (2006).
Marco D. Santambrogio is a senior member of the IEEE. Marco D. Santambrogio is a senior member of both the IEEE and ACM, he is member of the IEEE Computer Society (CS) and the IEEE Circuits and Systems Society (CAS). He is or has been member of different program committees of electronic design automation conferences, among which: DAC, DATE, CODES+ISSS, FPL, RAW, EUC, IFIP VLSI Conference.
He has been with the Micro Architectures Laboratory at the Politecnico di Milano, where he founded the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, in charge of the laboratory.
Contact details
If you have any enquiries about the course or if you need technical assistance please contact pok@polimi.it. For further information, see FAQ page.