This course, which is the fourth one of a “series”, is for anyone passionate about practicing how to develop FPGA-accelerated applications with SDAccel.
Introduction to FPGA systems
This series of courses introduces students to the concept of Reconfigurable FPGA-based Systems, by discussing their overall architecture and companion design flows.
The goal is to present to the students the methodological approaches for the design of such systems, showing also real industrial tools, examples and common practices.
See the other MOOCs of the series.
If you are a POLIMI student you have to log in using your Person Code. This is the only way to prove your participation in this course for official recognition.
This course will present several scenarios where the workloads require more performance than can be obtained even by using the fastest CPUs.
This scenario is turning cloud and data center architectures toward accelerated computing.
Within this course we are going to show you how to gain benefits by using Xilinx SDAccel to program Amazon EC2 F1 instances.
We are going to do this through a working example of an algorithm used in computational biology.
The huge amount of data they need to process and the complexity of these algorithms, raised the problem of increasing the amount of computational power needed to perform the computation.
In this scenario, hardware accelerators revealed to be efficient in achieving a speed-up in the computation while, at the same time, saving power consumption.
Among the algorithms used in computational biology, the Smith-Waterman algorithm is a dynamic programming algorithm, guaranteed to find the optimal local alignment
between two strings that could be nucleotides or proteins.
In the following classes we presented an analysis and successive FPGA-based hardware acceleration of the Smith-Waterman algorithm used to perform pairwise alignment of DNA sequences.
Within this context, this course is focusing on distributed, heterogeneous cloud infrastructures, providing you details on how to use Xilinx SDAccel, through working examples,
to bring your solutions to life by using the Amazon EC2 F1 instances.
This course follows the previous ones “FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing”, “FPGA computing systems: Partial Dynamic Reconfiguration” and “Developing FPGA-accelerated cloud applications with SDAccel: Theory”.
Within this context no specific background knowledge is requested. Anyone with moderate computer experience should be able to master the materials in this course.
A Forum section is available. The Forum is designed to allow students to exchange opinions and discuss open questions.
The instructors participate in the Forum as well, as Administrators, and oversee the developing of the threads.
Quizzes and scores
The course is organized into different weeks and modules. You will find some quizzes to check your understanding.
The final grade for the course will be calculated based on your performance in the quizzes.
Certificate of Accomplishment
The Certificate of Accomplishment will be released to anyone who successfully completes the course by answering correctly to at least 60% of the questions by the end of the edition. You will be able to download the Certificate of Accomplishment directly on the website.
Once you have successfully passed the course, you can request the Certificate of Accomplishment without waiting for the end of the edition.
The Certificate of Accomplishment does not confer any academic credit, grade or degree.
For further information, see FAQ page.
Lorenzo Di Tucci
Lorenzo is a Ph.D. Student at Politecnico di Milano and co-founder of Huxelerate.
He received his Bachelor’s and Master’s degrees in Computer Engineering from Politecnico di Milano in 2013 and 2016 respectively. In 2016 he received a Master of Science in Computer Science from the University of Illinois at Chicago.
Lorenzo has been a Research Assistant at the University of Illinois at Chicago, Visiting Researcher at Lawrence Berkeley National Laboratory in Berkeley (CA) and Rocca Fellow at Massachusetts Institute of Technology in Cambridge (MA).
His research interests float around FPGA design, High-Performance Computing, and Hardware Architectures.
Marco Domenico Santambrogio
He is an Associate professor at Politecnico di Milano and a Research Affiliate with the CSAIL at MIT. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), his second M. Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). Dr. Santambrogio was a postdoc fellow at CSAIL, MIT, and he has also held visiting positions at the Department of Electrical Engineering and Computer Science of the Northwestern University (2006 and 2007) and Heinz Nixdorf Institut (2006).
Marco D. Santambrogio is a senior member of the IEEE. Marco D. Santambrogio is a senior member of both the IEEE and ACM, he is member of the IEEE Computer Society (CS) and the IEEE Circuits and Systems Society (CAS). He is or has been member of different program committees of electronic design automation conferences, among which: DAC, DATE, CODES+ISSS, FPL, RAW, EUC, IFIP VLSI Conference.
He has been with the Micro Architectures Laboratory at the Politecnico di Milano, where he founded the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, in charge of the laboratory.