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Politecnico di Milano

Developing FPGA-accelerated cloud applications with SDAccel: Theory

This course, which is the third one of a “series”, is for anyone passionate about learning the theory on how to develop FPGA-accelerated applications with SDAccel.

Introduction to FPGA systems

This series of courses introduces students to the concept of Reconfigurable FPGA-based Systems, by discussing their overall architecture and companion design flows. The goal is to present to the students the methodological approaches for the design of such systems, showing also real industrial tools, examples and common practices.

See the other MOOCs of the series.

If you are a POLIMI student you have to log in using your Person Code. This is the only way to prove your participation in this course for official recognition.

Course description

We are entering an era in which technological progress induces paradigm shifts in computing.

As a tradeoff between the two extreme characteristics of GPP and ASIC, we can find a new concept, a new idea of computing... the reconfigurable computing, which has combined the advantages of both the previous worlds. Within this context, we can say that reconfigurable computing will widely, pervasively, and gradually impact human lives. Hence, it is time that we focus on how reconfigurable computing and reconfigurable system design techniques are to be utilised for building applications.

On one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance.

Within this context, the Xilinx SDx tools, including the SDAccel environment, the SDSoC environment, and Vivado HLS, provide an out-of-the-box experience for system programmers looking to partition elements of a software application to run in an FPGA-based hardware element, and having that hardware work seamlessly with the rest of the application running in a processor or embedded processor.

The out-of-the-box experience will provide interesting and, let us say, “good enough” results for many applications.

However, this may not be true for you, you may be looking for better performance, data throughput, reduced latency, or to reduce the resources usage...

This course is focusing on this. After introducing you to the FPGAs we are going to dig more into the details on how to use Xilinx SDAccel providing you also with working examples on how to optimize the hardware logic to obtain the best of of your hardware implementations. In this case, certain attributes, directives, or pragmas, can be used to direct the compilation and synthesis of the hardware kernel, or to optimise the function of the data mover operating between the processor and the hardware logic.

Furthermore, in this course we are going to focus on distributed, heterogeneous infrastructures, presenting how to bring your solutions to life by using the Amazon EC2 F1 instances.


This course follows the previous ones “FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing” and “FPGA computing systems: Partial Dynamic Reconfiguration”. Within this context no specific background knowledge is requested. Anyone with moderate computer experience should be able to master the materials in this course.

Discussion forum

A Forum section is available. The Forum is designed to allow students to exchange opinions and discuss open questions. The instructors participate in the Forum as well, as Administrators, and oversee the developing of the threads.

Quizzes and scores

The course is organized into different weeks and modules. You will find some quizzes to check your understanding. The final grade for the course will be calculated based on your performance in the quizzes.

Certificate of Accomplishment

The Certificate of Accomplishment will be released to anyone who successfully completes the course by answering correctly to at least 60% of the questions by the end of the edition. You will be able to download the Certificate of Accomplishment directly on the website.

Once you have successfully passed the course, you can request the Certificate of Accomplishment without waiting for the end of the edition.

The Certificate of Accomplishment does not confer any academic credit, grade or degree.


For further information, see FAQ page.

Course Faculty

Lorenzo Di Tucci

Lorenzo Di Tucci

Lorenzo is a Ph.D. Student at Politecnico di Milano and co-founder of Huxelerate.

He received his Bachelor’s and Master’s degrees in Computer Engineering from Politecnico di Milano in 2013 and 2016 respectively. In 2016 he received a Master of Science in Computer Science from the University of Illinois at Chicago.

Lorenzo has been a Research Assistant at the University of Illinois at Chicago, Visiting Researcher at Lawrence Berkeley National Laboratory in Berkeley (CA) and Rocca Fellow at Massachusetts Institute of Technology in Cambridge (MA). His research interests float around FPGA design, High-Performance Computing, and Hardware Architectures.

Marco Santambrogio

Marco Domenico Santambrogio

He is an Associate professor at Politecnico di Milano and a Research Affiliate with the CSAIL at MIT. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), his second M. Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). Dr. Santambrogio was a postdoc fellow at CSAIL, MIT, and he has also held visiting positions at the Department of Electrical Engineering and Computer Science of the Northwestern University (2006 and 2007) and Heinz Nixdorf Institut (2006).

Marco D. Santambrogio is a senior member of the IEEE. Marco D. Santambrogio is a senior member of both the IEEE and ACM, he is member of the IEEE Computer Society (CS) and the IEEE Circuits and Systems Society (CAS). He is or has been member of different program committees of electronic design automation conferences, among which: DAC, DATE, CODES+ISSS, FPL, RAW, EUC, IFIP VLSI Conference.

He has been with the Micro Architectures Laboratory at the Politecnico di Milano, where he founded the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, in charge of the laboratory.

  1. Classes Start

    May 09, 2022
  2. Classes End

    May 28, 2023
  3. Length

    6 Weeks
  4. Estimated Effort

    4-10 hours/week
  5. Language

  6. Course Number

  7. MOOCs For Master of science